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STLC3085
Integrated Pots Interface for Home Access Gateway and WLL
Preliminary Data
Features

Monochip SLIC optimised for WLL & VoIP applications Implement all key features of the borsht function Single supply (4.5 to 12V) Built in DC/DC Converter controller Soft battery reversal with programmable transition time On-hook transmission Programmable off-hook detector threshold Integrated ringing Integrated ring trip Parallel control interface (3.3V logic level) Programmable constant current feed Surface mount package Integrated thermal protection Dual gain value option Automatic recognition flyback and buckboost configuration BCDIIIS 90V technology -40 to +85C operating range is the ability to operate with a single supply voltage (from +4.5V to +12V) and self generate the negative battery by means of an on chip DC/ DC converter controller that drives an external MOS switch. The battery level is properly adjusted depending on the operating mode. A useful characteristic for these applications is the integrated ringing generator. The control interface is a parallel type with open drain output and 3.3V logic levels. Constant current feed can be set from 20mA to 25mA. Off-hook detection threshold is programmable from 5mA to 9mA. The device, developed in BCDIIIS technology (90V process), operates in the extended temperature range and integrates a thermal protection that sets the device in power down when Tj exceeds 140C..
TQFP44
Description
The STLC3085 is a SLIC device specifically designed for WLL (Wireless Local Loop), and ISDN Terminal Adaptors and VoIP applications. One of the distinctive characteristic of this device
Order codes
Part number E-STLC3085 (*)
(*) ECOPACK(R) (see Section 5)
Temp range, C -40 to 85
Package TQFP44
Packing Tube
February 2006
Rev 1
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Contents
STLC3085
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 1.2 1.3 1.4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 2.2 2.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 3.2 DC/DC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 Power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 High impedance feeding (HI-Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Layout recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 External components list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4
Applications diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Appendix A STLC3085 test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Appendix B STLC3085 overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Appendix C Typical state diagram for STLC3085 operation . . . . . . . . . . . . . . . . 25 5 6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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STLC3085
Block diagram and pin description
1
1.1
Block diagram and pin description
Block diagram
Figure 1. Block diagram
D0 D1 D2 DET
INPUT LOGIC AND DECODER
OUTPUT LOGIC
BGND
Status and functions
TIP TX RX ZAC1 ZAC RS ZB
LINE OUTPUT
SUPERVISION AC PROC
DRIVER
STAGE
RING
CREV
DC PROC
CSVR
CLK RSENSE GATE VF
DC/DC CONV.
REFERENCE
Vcc Vss
Agnd
CVCC VPOS
VOLT.
REG.
VBAT
Vbat
CAC
ILTF RD IREF RLIM RTH
AGND
1.2
Pin connection
Figure 2. Pin connection
VBAT1 BGND 35 CREV VBAT N.C. CSVR 34 33 32 31 30 29 28 27 26 25 24 23 12 RES 13 RX 14 ZAC1 15 ZAC 16 RS 17 ZB 18 CAC 19 TX 20 CZ 21 VF 22 N.C. ILTF RD RTH IREF RLIM AGND CVCC VPOS RSENSE GATE CLK RING 37 N.C. N.C. N.C. 38 TIP
44 D0 D1 D2 PD GAIN SET N.C. DET RES RES RES RES 1 2 3 4 5 6 7 8 9 10 11
43
42
41
40
39
36
D00TL488
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Block diagram and pin description
STLC3085
1.3
Table 1.
N 1 2 3 4 5 6,22,38, 39,40,42 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Pin description
Pin description
Pin D0 D1 D2 PD Gain SET Control Interface: input bit 0. Control Interface: input bit 1. Control interface: input bit 2. Power Down input. Normally connected to CVCC (or to logic level high). Control gain interface: 0 Level Rxgain = 0dB Txgain = -6dB Function
1 Level Rxgain = +6dB Txgain = -12dB Not connected. Logic interface output of the supervision detector (active low).
NC DET
RESERVED Connected to GND RESERVED Connected to GND RESERVED Connected to GND RESERVED Left open. RESERVED Connected to GND RX ZAC1 ZAC RS ZB CAC TX CZ VF 4 wire input port (RX input); 300K input impedance. This signal is referred to AGND. If connected to single supply CODEC output it must be DC decoupled with proper capacitor. RX buffer output (the AC impedance is connected from this node to ZAC). AC impedance synthesis. Protection resistors image (the image resistor is connected from this node to ZAC). Balance Network for 2 to 4 wire conversion (the balance impedance ZB is connected from this node to AGND. ZA impedance is connected from this node to ZAC1). AC feedback input, AC/DC split capacitor (CAC). 4 wire output port (TX output). The signal is referred to AGND. If connected to single supply CODEC input it must be DC decoupled with proper capacitor. Fly-Back compensation Feedback input for DC/DC converter controller. Power Switch Controller Clock (typ. 125KHz). This pin can also be connected to CVCC or AGND. When the CLK pin is connected to CVCC an internal auto-oscillation is internally generated and it is used instead of the external clock. When the CLK pin is connected to AGND, the GATE output is disabled. Driver for external Power MOS transistor (P-chanell in Buck-boost configuration, Nchannel in Fly-back configuration). Voltage input for current sensing. RSENSE resistor should be connected close to this pin and VPOS pin (Buck-boost) or GND (Fly-back). The PCB layout should minimize the extra resistance introduced by the copper tracks.
23
CLK
24
GATE
25
RSENSE
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STLC3085
Table 1.
N 26 27 28 29 30 31 32 33 34 35 36 37 41 43 44
Block diagram and pin description
Pin description (continued)
Pin VPOS CVCC AGND RLIM IREF RTH RD ILTF CSVR BGND VBAT RING TIP CREV VBAT1 Positive supply input. Internal positive voltage supply filter. Analog Ground, must be shorted with BGND. Constant current feed programming pin (via RLIM). RLIM should be connected close to this pin and AGND pin to avoid noise injection. Internal bias current setting pin. RREF should be connected close to this pin and AGND pin to avoid noise injection. Off-hook threshold programming pin (via RTH). RTH should be connected close to this pin and AGND pin to avoid noise injection. DC feedback and ring trip input. RD should be connected close to this pin and AGND pin to avoid noise injection. Transversal line current image output. Battery supply filter capacitor. Battery Ground, must be shorted with AGND. Regulated battery voltage self generated by the device via DC/DC converter. Must be shorted to VBAT1. 2 wire port; RING wire (Ib is the current sunk into this pin). 2 wire port; TIP wire (Ia is the current sourced from this pin). Reverse polarity transition time control. A proper capacitor connected between this pin and AGND is setting the reverse polarity transition time. This is the same transition time used to shape the "trapezoidal ringing" during ringing injection. Frame connection. Must be shorted to VBAT. Function
1.4
Thermal data
Table 2.
Symbol Rth j-amb
Thermal data
Parameter Thermal Resistance Junction to Ambient Typ. Value 60 Unit C/W
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Electrical specification
STLC3085
2
2.1
Electrical specification
Absolute maximum ratings
Table 3.
Symbol Vpos A/BGND Vdig Tj Vbtot ESD RATING Positive Supply Voltage AGND to BGND Pin D0, D1, D2, DET Max. junction Temperature Vbtot=|Vpos|+|Vbat|. (Total voltage applied to the device supply pins). Human Body Model Charged Device Model
Absolute maximum ratings
Parameter Value -0.4 to +13 -1 to +1 -0.4 to 5.5 150 85 1750 500 Unit V V V C V V V
2.2
Operating range
Table 4. Operating range
Symbol Vpos A/BGND Vdig Top Vbat (1) Positive Supply Voltage AGND to BGND Pin D0, D1, D2, DET, PD Ambient Operating Temperature Range Self Generated Battery Voltage Parameter Value 4.5 to +12 -100 to +100 -0.25 to 5.25 -40 to +85 -64 max. Unit V mV V C V
(1) Vbat is self generated by the on chip DC/DC converter and can be programmed via RF1 and RF2. RF1 and RF2 shall be selected in order to fulfil the a.m limits (see Table 10 )
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STLC3085
Electrical specification
2.3
Table 5.
Electrical characteristics
Electrical characteristics
Test conditions: Vpos = 6.0V, AGND = BGND, Normal Polarity, Tamb = 25C. External components as listed in the "Typical Values" column of EXTERNAL COMPONENTS Table. Note: Testing of all parameter is performed at 25C. Characterisation as well as design rules used allow correlation of tested performances at other temperatures. All parameters listed here are met in the operating range: -40 to +85C. Symbol Parameter Test Condition Min. Typ. Max. Unit
DC CHARACTERISTICS Il = 0, HI-Z (High impedance feeding) Tamb = 0 to 85C Il = 0, HI-Z (High impedance feeding) Tamb = -40 to 85C Il = 0, ACTIVE Tamb = 0 to 85C Il = 0, ACTIVE Tamb = -40 to 85C ACTIVE mode ACTIVE mode. Rel. to programmed value 20mA to 25mA HI-Z (High Impedance feeding)
Vlohi
Line voltage
40
46
V
Vlohi
Line voltage
38
44
V
Vloa Vloa Ilim
Line voltage
31
38
V
Line voltage Lim. current programming range Lim. current accuracy Feeding resistance
29 20
35 25
V mA
Ilima Rfeed HI
-10 2.4
10 3.6
% k
AC CHARACTERISTICS Rp = 50, 1% tol., L/T Long. to transv. (see Appendix for test circuit) ACTIVE N. P., RL = 600 (1) f = 300 to 3400Hz Rp = 50, 1% tol., T/L Transv. to long. (see Appendix for test circuit) ACTIVE N. P., RL = 600 (1) f = 300 to 3400Hz Rp = 50, 1% tol., T/L Transv. to long. (see Appendix for test circuit) ACTIVE N. P., RL = 600 (1) f = 1kHz 300 to 3400Hz, 2WRL 2W return loss ACTIVE N. P., RL = 600 (1) 300 to 3400Hz, 20Log|VRX/VTX|, ACTIVE N. P., RL = 600
(1)
50
58
dB
40
45
dB
48
53
dB
22
26
dB
THL
Trans-hybrid loss
30
dB
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Electrical specification
STLC3085
Table 5.
Electrical characteristics (continued)
Test conditions: Vpos = 6.0V, AGND = BGND, Normal Polarity, Tamb = 25C. External components as listed in the "Typical Values" column of EXTERNAL COMPONENTS Table. Note: Testing of all parameter is performed at 25C. Characterisation as well as design rules used allow correlation of tested performances at other temperatures. All parameters listed here are met in the operating range: -40 to +85C. Symbol Ovl TXoff G24 Parameter 2W overload level TX output offset Transmit gain abs. Test Condition at line terminals on ref. imped. ACTIVE N. P., RL = 600 (1) ACTIVE N. P., RL = 600 (1) 0dBm @ 1020Hz, ACTIVE N. P., RL = 600 (1) 0dBm @ 1020Hz, G42 Receive gain abs. ACTIVE N. P., RL = 600 (1) rel. 1020Hz; 0dBm, 300 to 3400Hz, ACTIVE N. P., RL = 600 (1) rel. 1020Hz; 0dBm, 300 to 3400Hz, ACTIVE N. P., RL = 600 (1) psophometric filtered V2Wp Idle channel noise at line 0dB gainset ACTIVE N. P., RL = 600 (1) Tamb = 0 to +85C psophometric filtered V2Wp Idle channel noise at line 0dB gainset ACTIVE N. P., RL = 600 (1) Tamb = -40 to +85C psophometric filtered V4Wp Idle channel noise at line 0dB gainset ACTIVE N. P., RL = 600 (1) Tamb = 0 to +85C psophometric filtered V4Wp Idle channel noise at line 0dB gainset Total Harmonic Distortion CLK operating range ACTIVE N. P., RL = 600 (1) Tamb = -40 to +85C ACTIVE N. P., RL = 600 (1) -10% 125 -44 10% dB kHz -75 dBmp -75 -70 dBmp -68 dBmp -73 -68 dBmp -0.4 0.4 dB -6.4 -5.6 dB 3.2 -250 250 dBm mV Min. Typ. Max. Unit
G24f
TX gain variation vs. freq.
-0.12
0.12
dB
G24f
RX gain variation vs. freq.
-0.12
0.12
dB
Thd CLKfreq RING
Vring
Line voltage
RING D2 toggling @ fr = 25Hz Load = 2REN; Crest Factor = 1.25 1REN = 1800 + 1.0F Tamb = 0 to +85C
41
45
Vrms
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STLC3085
Table 5. Electrical characteristics (continued)
Electrical specification
Test conditions: Vpos = 6.0V, AGND = BGND, Normal Polarity, Tamb = 25C. External components as listed in the "Typical Values" column of EXTERNAL COMPONENTS Table. Note: Testing of all parameter is performed at 25C. Characterisation as well as design rules used allow correlation of tested performances at other temperatures. All parameters listed here are met in the operating range: -40 to +85C. Symbol Parameter Test Condition RING D2 toggling @ fr = 25Hz Load = 2REN; Crest Factor = 1.25 1REN = 1800 + 1.0F Tamb = -40 to +85C Min. Typ. Max. Unit
Vring
Line voltage
40
44
Vrms
DETECTORS IOFFTHA ROFTHA IONTHA RONTHA IOFFTHI ROFFTHI IONTHI RONTHI Irt Irta Trtd Td Rlrt (2) ThAl Off/hook current threshold Off/hook loop resistance threshold On/hook current threshold On/hook loop resistance threshold Off/hook current threshold Off/hook loop resistance threshold On/hook current threshold On/hook loop resistance threshold Ring Trip detector threshold range Ring Trip detector threshold accuracy Ring trip detection time Dialling distortion Loop resistance Tj for th. alarm activation 160 ACT. mode, RTH = 32.4k 1% (Prog. ITH = 9mA) ACT. mode, RTH = 32.4k 1% (Prog. ITH = 9mA) ACT. mode, RTH = 32.4k 1% (Prog. ITH = 9mA) ACT. mode, RTH = 32.4k 1% (Prog. ITH = 9mA) Hi Z mode, RTH = 32.4k 1% (Prog. ITH = 9mA) Hi Z mode, RTH = 32.4k 1% (Prog. ITH = 9mA) Hi Z mode, RTH = 32.4k 1% (Prog. ITH = 9mA) Hi Z mode, RTH = 32.4k 1% (Prog. ITH = 9mA) RING RING RING ACTIVE -1 8 20 -15 TBD 1 500 50 15 8 10.5 800 6 10.5 3.4 6 mA k mA k mA W mA k mA % ms ms W C
DIGITAL INTERFACE INPUTS: D0, D1, D2, PD, CLK OUTPUTS: DET Vih Vil In put high voltage Input low voltage 2 0.8 V V
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Electrical specification
STLC3085
Table 5.
Electrical characteristics (continued)
Test conditions: Vpos = 6.0V, AGND = BGND, Normal Polarity, Tamb = 25C. External components as listed in the "Typical Values" column of EXTERNAL COMPONENTS Table. Note: Testing of all parameter is performed at 25C. Characterisation as well as design rules used allow correlation of tested performances at other temperatures. All parameters listed here are met in the operating range: -40 to +85C. Symbol Iih Iil Vol Parameter Input high current Input low current Output low voltage Iol = 1mA Test Condition Min. -10 -10 Typ. Max. 10 10 0.45 Unit A A V
PSRR AND POWER CONSUMPTION PSERRC Power supply rejection Vpos to Vripple = 100mVrms 2W port 50 to 4000Hz Vpos supply current @ ii = 0 HI-Z On-Hook ACTIVE On-Hook, RING (line open) RING Off-Hook RSENSE = 130m -20% 26 36 13 50 55 770 25 80 90 +20% dB mA mA mA mApk
Ivpos
Ipk (3)
Peak current limiting accuracy
(1) RL: Line Resistance (2) Rlrt = Maximum loop resistance (incl. telephone) for correct ring trip detection. (3) Buck Boost configuration.
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STLC3085
Functional description
3
Functional description
The STLC3085 is a device specifically developed for WLL VoIP and ISDN-TA applications. It is based on a SLIC core, on purpose optimised for these applications, with the addition of a DC/DC converter controller to fulfil the WLL and ISDN-TA design requirements. The SLIC performs the standard feeding, signalling and transmission functions. It can be set in three different operating modes via the D0, D1, D2 pins of the control logic interface (0 to 3.3V logic levels). The loop status is carried out on the DET pin (active low). The DET pin is an open drain output to allow easy interfacing with both 3.3V and 5V logic levels. The four possible SLIC's operating modes are:

Power Down High Impedance Feeding (HI-Z) Active Ringing
Table 6 shows how to set the different SLIC operating modes. Table 6.
PD 0 1 1 1
SLIC operating modes.
D0 0 0 0 0 D1 0 0 1 1 D2 X X 0 1 Power Down H.I. Feeding (HI-Z) Active Normal Polarity Active Reverse Polarity Not used Not used Operating Mode
1
1
0
0/1
Ring (D2 bit toggles @ fring)
3.1
DC/DC converter
The DC/DC converter controller is driving an external power MOS transistor N-Ch plus transformer (Flyback configuration) or P-Ch plus inductor (BuckBoost configuration), in order to generate the negative battery voltage needed for device operation. The DC/DC converter controller is synchronised with an external CLK (125KHz typ.) or with an internal clock generated when the pin CLK is connected to CVCC. One Rsense in series to PGND supply (FlyBack) or to VPOS supply (BuckBoost) allows to fix the maximum allowed input peak current. This feature is implemented in order to avoid overload on Vpos supply in case of line transient (ex. ring trip detection). Typ. value of 130m guarantees an average current consumption from Vpos < 600mA for BuckBoost configuration and < 1.25A for Fly- Back configuration.
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Functional description
STLC3085
Typ. value of 220m guarantees an average current consumption from Vpos < 800mA for FlyBack configuration The self generated battery voltage is set to a predefined value in on-hook state. This value can be adjusted via one external resistor (RF1) and it is typical -46V. When RING mode is selected this value is increased to -64V typ. Once the line goes in off-hook condition, the DC/DC converter automatically adjusts the generated battery voltage in order to feed the line with a fixed DC current (programmable via RLIM) optimising the power dissipation.
3.2
3.2.1
Operating modes
Power down
When this mode is selected the SLIC is switched off and the TIP and RING pins are in high impedance. Also the line detectors are disabled therefore the off-hook condition cannot be detected. This mode can be selected in emergency condition when it is necessary to cut any current delivered to the line. This mode is also forced by STLC3085 in case of thermal overload (Tj > 140C). In this case the device goes back to the previous status as soon as the junction temperature decrease under the hysteresis threshold. No AC transmission is possible
3.2.2
High impedance feeding (HI-Z)
This operating mode is normally selected when the telephone is in on-hook in order to monitor the line status keeping the power consumption at the minimum. The output voltage in on-hook condition is equal to the self generated battery voltage (-46V typ). When off-hook occurs the DET becomes active (low logic level). The off-hook threshold in HI-Z mode is the same value as programmed in ACTIVE mode. The DC characteristic in HI-Z mode is just equal to the self generated battery with 2x(1600+Rp) in series (see Figure 3), where Rp is the external protection resistance. No AC transmission is possibile. Figure 3. DC Characteristic in HI-Z Mode.
IL Vbat 2x(R1+Rp)
Slope: 2x(R1+Rp) (R1=1500ohm)
VL Vbat (-46V)
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STLC3085
Functional description
3.2.3
Active
3.2.3.1 DC characteristics & supervision
When this mode is selected the STLC3085 provides both DC feeding and AC transmission. The STLC3085 feeds the line with a constant current fixed by RLIM (20mA to 25mA range). The on-hook voltage is typically 38V allowing on-hook transmission; the self generated Vbat is 46V typ. If the loop resistance is very high and the line current cannot reach the programmed constant current feed value, the STLC3085 behaves like a 38V voltage source with a series impedance equal to the protection resistors 2xRp (typ. 2x50). Figure 4 shows the typical DC characteristic in ACTIVE mode. The line status (on/off hook) is monitored by the SLIC'S supervision circuit. The off-hook threshold can be programmed via the external resistor RTH in the range from 5mA to 9mA. Independently on the programmed constant current value, the TIP and RING buffers have a current source capability limited to 65mA typ. Figure 4. DC characteristic in ACTIVE mode
IL Ilim (20 to 25mA)
2Rp
10V
VL
Vbat (-46V)
Moreover the power available at Vbat is controlled by the DC/DC converter that limits the peak current drawn from the Vpos supply. The maximum allowed current peak is set by RSENSE resistor.
3.2.3.2 AC characteristics
The SLIC provides the standard SLIC transmission functions: Once in active mode the SLIC can operate with two different Tx, Rx Gain. Setting properly by the Gain set control bit (see Table 7). Table 7. Gain Set in Active Mode
4 to 2 wire Gain 0dB +6dB 2 to 4 wire Gain -6dB -12dB Impedance Synthesis Scale Factor x 50 x 25
Gain set 0 1
Input impedance synthesis: can be real or complex and is set by a scaled (x50 or x25) external ZAC impedance.
13/28
Functional description
STLC3085
Transmit and receive: The AC signal present on the 2W port (TIP/RING) is transferred to the TX output with a -6dB or -12dB gain and from the RX input to the 2W port with a 0dB or +6dB gain. 2 to 4 wire conversion: The balance impedance can be real or complex, the proper cancellation is obtained by means of two external impedance ZA and ZB
Once in Active mode (D1=1) the SLIC can operate in different states setting properly D0 and D2 control bits (see also Table 8). Table 8.
D0 0 0
SLIC states in ACTIVE mode
D1 1 1 D2 0 1 Active Normal Polarity Active Reverse Polarity Operating Mode
3.2.3.3 Polarity reversal
The D2 bit controls the line polarity, the transition between the two polarities is performed in a "soft" way. This means that the TIP and RING wire exchange their polarities following a ramp transition (see Figure 5). The transition time is controlled by an external capacitor CREV. This capacitor is also setting the shape of the ringing trapezoidal waveform. When the control pins set battery reversal the line polarity is reversed with a proper transition time set via an external capacitor (CREV). Figure 5. TIP/RING typical transition from Direct to Reverse Polarity
GND TIP
4V typ.
38 V typ ON-HOOK
dV/dT set by CREV RING
3.2.4
Ringing
When this mode is selected STLC3085 self generate an higher negative battery (-64V typ.) in order to allow a balanced ringing signal of typically 59Vpeak. In this condition both the DC and AC feedback loop are disabled and the SLIC line drivers operate as voltage buffers. The ring waveform is obtained toggling the D2 control bit at the desired ring frequency. This bit in fact controls the line polarity (0=direct; 1= reverse). As in the ACTIVE mode the line voltage transition is performed with a ramp transition, obtaining in this way a trapezoidal balanced ring waveform (see Figure 6). The shaping is defined by the CREV external capacitor.
14/28
STLC3085
Figure 6. TIP/RING typical ringing waveform
GND TIP
2.5V typ.
Functional description
59V typ.
dV/dT set by CREV RING VBAT
2.5V typ.
Selecting the proper capacitor value it is possible to get different crest factor values. The following table shows the crest factor values obtained with a 20Hz and 25Hz ring frequency and with 1REN. These value are valid either with European or USA specification: Table 9.
CREV 22nF 27nF 33nF
(1) Distorsion already less than 10%.
CREST FACTOR @20Hz 1.2 1.25 1.33
CREST FACTOR @25Hz 1.26 1.32 Not significant (1)
The ring trip detection is performed sensing the variation of the AC line impedance from on hook (relatively high) to off-hook (low). This particular ring trip method allows to operate without DC offset superimposed on the ring signal and therefore obtaining the maximum possible ring level on the load starting from a given negative battery. It should be noted that such a method is optimised for operation on short loop applications and may not operate properly in presence of long loop applications (> 500). Once ring trip is detected, the DET output is activated (logic level low), at this point the card controller or a simple logic circuit should stop the D2 toggling in order to effectively disconnect the ring signal and then set the STLC3085 in the proper operating mode (normally ACTIVE).
3.2.4.1 Ring level in presence of more telephone in parallel
As already mentioned above the maximum current that can be drawn from the Vpos supply is controlled and limited via the external RSENSE. This will limit also the power available at the self generated negative battery. If for any reason the ringer load is too low the self generated battery will drop in order to keep the power consumption to the fixed limit and therefore also the ring voltage level will be reduced. In the typical Buck Boost configuration with RSENSE = 130m the peak current from Vpos is limited to about 770mA, which correspond to an average current of 600mA max. In this condition the STLC3085 can drive up to 2REN with a ring frequency fr=25Hz (1REN = 1800 + 1.0F, European standard). In Fly-Back configuration the value of RSENSE = 220m guarantees match both European and USA standards.
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Functional description
STLC3085
3.2.5
Layout recommendation
A properly designed PCB layout is a basic issue to guarantee a correct behaviour and good noise performances. Particular care must be taken on the ground connection and in this case the star configuration allows surely to avoid possible problems (see Application Diagram Figure 7 and Figure 8). The ground of the power supply (VPOS) has to be connected to the center of the star, let's call this point SYSTEM-GND. This point should show a resistance as low as possible, that means it should be a ground plane. In particular to avoid noise problems the layout should prevent any coupling between the DC/ DC converter components and analog pins that are referred to AGND (ex: RD, IREF, RTH, RLIM, VF). As a first reccomendation the components CV, L, T1, D1, CVPOS, RSENSE should be kept as close as possible to each other and isolated from the other components. Additional improvements can be obtained:

decoupling the center of the star from the analog ground of STLC3085 using small chokes. adding a capacitor in the range of 100nF between VPOS and AGND in order to filter the switch frequency on VPOS.
3.2.6
External components list
In order to properly define the external components value the following system parameters have to be defined:

The AC input impedance shown by the SLIC at the line terminals "Zs" to which the return loss measurement is referred. It can be real (typ. 600) or complex. The AC balance impedance, it is the equivalent impedance of the line "Zl" used for evaluation of the trans-hybrid loss performances (2/4 wire conversion). It is usually a complex impedance. The value of the two protection resistors Rp in series with the line termination. The slope of the ringing waveform "VTR/T ". The value of the constant current limit current "Ilim". The value of the off-hook current threshold "ITH". The value of the ring trip rectified average threshold current "IRTH". The value of the required self generated negative battery "VBATR" in ring mode (max value is 64V). This value can be obtained from the desired ring peak level + 5V. The value of the maximum current peak drawn from Vpos "IPK".

Table 10.
Name
External Components
Function Formula Typ. Value
BUCKBOOST CONFIGURATION RREF Bias setting current RREF = 1.3/Ibias Ibias = 50A CSVR = 1/(2 fp 1.8M) fp = 50Hz 26k 1% 1.5nF 10% 100V
CSVR
Negative Battery Filter
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STLC3085
Table 10.
Name RD
Functional description
External Components (continued)
Function Ring Trip threshold setting resistor AC/DC split capacitance Line protection resistor Current limiting programming Rp > 30 RLIM = 1300/Ilim 32.5k < RLIM < 65k Formula RD = 100/IRTH 2K < RD < 5K Typ. Value 4.12k 1% @ IRTH = 24mA 22F 20% 15V @ RD = 4.12k 50 1% 52.3k 1% @ Ilim = 25mA 32.4k 1% @ITH = 9mA 22nF 10% 10V @ 12V/ms 100k 100nF 20% 10V 100F
CAC RP RLIM
RTH
Off-hook threshold programming RTH = 290/ITH (ACTIVE mode) 27k < RTH < 52k Reverse polarity transition time programming Pull up resistors Internally supply filter capacitor CREV = ((1/3750) * T/VTR)
CREV RDD CVCC
Positive supply filter capacitor CVpos(1) with low impedance for switch mode power supply CV(2) CVB CRD(3) Battery supply filter capacitor with low impedance for switch mode power supply High frequency noise filter High frequency noise filter RDS(ON)1.2,VDS = -100V Total gate charge=20nC max. with VGS=4.5V and VDS=1V ID>500mA Vr > 100V, tRR 50ns RSENSE = 100mV/IPK
100F 20% 100V 470nF 20% 100V 100nF 10% 15V Possible choiches: IRF9510 or IRF9520 or IRF9120 or equivalent SMBYW01-200 or equivalent 130m @IPK = 770mA 270k 1% @ VBATR = -64V 9.1k 1% DC resistance 0.1 L=100H SUMIDA CDRH125 or equivalent
Q1
DC/DC converter switch P ch. MOS transistor
D1
DC/DC converter series diode DC/DC converter peak current limiting Negative battery programming level Negative battery programming level DC/DC converter inductor
RSENSE
RF1
250KRF2 L(4)
FLY-BACK CONFIGURATION RREF Bias setting current RREF = 1.3/Ibias; Ibias = 50A 26k 1%
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Functional description
STLC3085
Table 10.
Name CSVR
External Components (continued)
Function Negative Battery Filter Ring Trip threshold setting resistor AC/DC split capacitance Line protection resistor Current limiting programming Rp > 30 RLIM = 1300/Ilim 52.3k < RLIM < 65k Formula CSVR = 1/(2 fp 1.8M) fp = 50Hz RD = 100/IRTH 2K < RD < 5K Typ. Value 1.5nF 10% 100V 4.12k 1% @ IRTH = 24mA 22F 20% 15V @ RD = 4.12k 50 1% 52.3k 1% @ Ilim = 25mA 32.4k 1% @ITH = 9mA 22nF 10% 10V @ 12V/ms 100k 100nF 20% 10V 100F
RD
CAC RP RLIM
RTH
Off-hook threshold programming RTH = 290/ITH (ACTIVE mode) 27k < RTH < 52k Reverse polarity transition time programming Pull up resistors Internally supply filter capacitor CREV = ((1/3750) * T/VTR)
CREV RDD CVCC
Positive supply filter capacitor CVpos(1) with low impedance for switch mode power supply CV(2) CVB CRD(3) CZ CSF RSF RSENSE Battery supply filter capacitor with low impedance for switch mode power supply High frequency noise filter High frequency noise filter Fly-Back compensation capacitor Sense Filter capacitor Sense Filter resistor DC/DC converter peak current limiting DC/DC converter switch Nchan MOS transistor RSENSE = 375mV/IPK RDS(ON)0.05,VDSS = 30V VDG=30V, ID = 6.5A Low threshold drive Vr > 350V, tRR 80ns Fly-Back transformer 4W, Turns Ratio 1:16 fro VPOS range from 4.5V to 8.5V Formula
100F 20% 100V 470nF 20% 100V 100nF 10% 15V 2.2nF, 20% 120pF, 20% 1k 220m @IPK = 1.7A STN4NF03L or equivalent SMBYTW01-400 or equivalent Tyco COEV MAGNETICS MGPWG-00007 Typ. Value
Q1
D1
DC/DC converter series diode
T1
DC/DC Converter transformer
Name
Function
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STLC3085
Table 10.
T1
Functional description
External Components (continued)
DC/DC Converter transformer Negative battery programming level Negative battery programming level Fly-Back transformer 4W, Turns Ratio 1:8 fro VPOS range from 8.5V to 12V 250KRF1 RF2
@Gain Set = 0
RS ZAC ZA(5) ZB(5) Protection resistance image Two wire AC impedance SLIC impedance balancing network Line impedance balancing network RS = 50 (2Rp) ZAC = 50 (Zs - 2Rp) ZA = 50 Zs ZB = 50 Zl fo = 250kHz CCOMP = 1/(2fo100(RP)) CH = CCOMP 5k @ Rp = 50 25k 1% @ Zs = 600 30k 1% @ Zs = 600 30k 1% @ Zl = 600
CCOMP AC feedback loop compensation CH Trans-Hybrid Loss frequency compensation
120pF 10% 10V @ Rp = 50 120pF 10% 10V
@Gain Set = 1
RS ZAC ZA(5) ZB(5) Protection resistance image Two wire AC impedance SLIC impedance balancing network Line impedance balancing network RS = 25 (2Rp) ZAC = 25 (Zs - 2Rp) ZA = 25 Zs ZB = 25 Zl fo = 250kHz CCOMP = 2/(2fo100(RP)) CH = CCOMP 2.55k @ Rp = 50 12.5k 1% @ Zs = 600 15k 1% @ Zs = 600 15k 1% @ ZI = 600 220pF 10% 10VL @ Rp = 50 220pF 10% 10V
CCOMP AC feedback loop compensation CH Trans-Hybrid Loss frequency compensation
(1) CVpos should be defined depending on the power supply current capability and maximum allowable ripple. (2) For low ripple application use 2x47 F in parallel. (3) Can be saved if proper PCB layout avoid noise coupling on RD pin (high impedance input). (4) For high efficiency in HI-Z mode coil resistance @125kHz must be < 3. (5) In case Zs=Zl, ZA and ZB can be replaced by two resistors of same value: RA=RB=|Zs|.
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Applications diagram
STLC3085
4
Applications diagram
Figure 7. Application Diagram with N-Channel
RX TX CVCC VPOS CVPOS
T1 RS RX RS ZAC CCOMP ZAC ZA ZB CH VDD RDD GAIN SET ZB VF CZ CZ RF2 VBAT CVB RF1 CV ZAC1 TX AGND BGND CVCC VPOS GATE RSF RSENSE CSF RSENSE D1 Q1 N-ch
STLC3085
CONTROL INTERFACE DET D0 D1 D2 PD DET D0 D1 D2 PD 8RES 9RES 10RES 12RES 11RES CAC ILTF RD
CLK RP TIP RP RING CSVR CREV
CLK TIP RING
CREV RTH RLIM IREF RREF RLIM
CSVR
RTH
RD AGND BGND SYSTEM GND SUGGESTED GROUND LAY-OUT CAC
CRD
D04TL626
PGND
Figure 8.
Application Diagram with P-Channel
CVCC RX TX VPOS CVPOS RSENSE
RS
RX RS ZAC
TX
AGND BGND
CVCC
VPOS RSENSE GATE D1 VBAT CVB RF1 CV RF2 L Q1 P-ch
CCOMP ZAC ZA
ZAC1
ZB CH VDD RDD ZB
VF
CLK GAIN SET
CLK RP TIP RP RING
STLC3085
CONTROL INTERFACE DET D0 D1 D2 PD DET D0 D1 D2 PD 8RES 9RES 10RES 12RES 11RES CAC ILTF RD
TIP RING
CSVR CREV CREV RTH RLIM IREF RREF RLIM RTH CSVR
RD AGND BGND SYSTEM GND SUGGESTED GROUND LAY-OUT CAC
CRD
D01TL494A
PGND
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STLC3085
STLC3085 test circuits
Appendix A STLC3085 test circuits
Referring to the application diagram shown in Figure 11 and using as external components the Typ. Values specified in the "External Components" Table 10 find below the proper configuration for each measurement. All measurements requiring DC current termination should be performed using "Wandel & Goltermann DC Loop Holding Circuit GH-1" or equivalent. Figure 9. 2W Return Loss 2WRL = 20Log(|Zref + Zs|/|Zref-Zs|) = 20Log(E/2Vs)
W&G GH1 Zref TIP 600ohm 100 F Vs 1Kohm E
100mA DC max Zin = 100K 200 to 6kHz
TX
STLC3085 application circuit
1Kohm
100 F RING RX
Figure 10. THL Trans Hybrid Loss THL = 20Log|Vrx/Vtx|
W&G GH1 TIP 100 F
100mA DC max Zin = 100K 200 to 6kHz
TX Vtx
600ohm
STLC3085 application circuit
100 F RING RX Vrx
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STLC3085 test circuits
STLC3085
Figure 11. G24 Transmit Gain G24 = 20Log|2Vtx/E|
W&G GH1 TIP 100 F
100mA DC max Zin = 100K 200 to 6kHz
TX Vtx
600ohm
STLC3085 application circuit
E 100 F RING RX
Figure 12. G42 Receive Gain G42 = 20Log|VI/Vrx|
W&G GH1 TIP 100 F Vl 600ohm
100mA DC max Zin = 100K 200 to 6kHz
TX
STLC3085 application circuit
100 F RING RX Vrx
Figure 13. PSRRC Power supply rejection Vpos to 2W port PSSRC = 20Log|Vn/Vl|
W&G GH1 TIP 100 F Vl 600ohm
100mA DC max Zin = 100K 200 to 6kHz
TX
STLC3085 application circuit
100 F RING VPOS RX
~
Vn
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STLC3085
Figure 14. L/T Longitudinal to Transversal Conversion L/T = 20Log|Vcm/Vl|
300ohm W&G GH1 100 F TIP 100 F
100mA DC max Zin = 100K 200 to 6kHz
STLC3085 test circuits
TX
Impedance matching better than 0.1%
Vcm
Vl
STLC3085 application circuit
100 F RING RX
300ohm
100 F
Figure 15. T/L Transversal to Longitudinal Conversion T/L = 20Log|Vrx/Vcm|
W&G GH1 TIP 100 F
100mA DC max Impedance matching better than 0.1% Zin = 100K 200 to 6kHz
300ohm
100 F
TX
STLC3085 application circuit
600ohm
Vcm
100 F RING RX Vrx
300ohm
100 F
Figure 16. V2Wp and W4Wp: Idle channel psophometric noise at line and TX. V2Wp = 20Log|Vl/0.774l|; V4Wp = 20Log|Vtx/0.774l|
W&G GH1 TIP 100 F
100mA DC max Zin = 100K 200 to 6kHz
TX Vtx psophometric filtered
600ohm Vl psophometric filtered
STLC3085 application circuit
100 F RING RX
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STLC3085 overvoltage protection
STLC3085
Appendix B STLC3085 overvoltage protection
Figure 17. Simplified configuration for indoor overvoltage protection
BGND
STPR120A
STLC3085N
TIP 2x SM6T39A RING RP1 RP1 RP2 RP2 TIP RING
VBAT STPR120A
RP1 = 30ohm: RP2 =Fuse or PTC > 20ohm
Figure 18. Standard overvoltage protection configuration for K20 compliance
BGND
STLC3085N
TIP 2x SM6T39A RP1
LCP1521S
RP2
TIP
RING
RP1
RP2
RING
VBAT
RP1 = 30ohm: RP2 =Fuse or PTC > 20ohm
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STLC3085
Typical state diagram for STLC3085 operation
Appendix C Typical state diagram for STLC3085 operation
Figure 19. Typical state diagram for STLC3085 operation
Normally used for On Hook Transmission PD=0, D0=D1=0 Power Down Active On Hook Ring Pause D0=0, D1=1, D2=0
Tj>Tth
Ring Burst
Ring Burst D0=1, D1=0, D2=0/1 PD=1, D0=D1=0 On Hook Detection for T>Tref HI-Z Feeding Active Off Hook Off Hook Detection D0=0, D1=1, D2=0 Ring Trip Detection Ringing
On Hook Condition
Off Hook Detection
Note: all state transitions are under the microprocessor control.
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Package information
STLC3085
5
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 20. TQFP44 (10x10x1.4mm) Mechanical Data & Package Dimensions
mm DIM. MIN. A A1 A2 B C D D1 D3 E E1 E3 e L L1 k 0.45 11.80 9.80 0.05 1.35 0.30 0.09 11.80 9.80 12.00 10.00 8.00 12.00 10.00 8.00 0.80 0.60 1.00 0.75 0.018 12.20 10.20 0.464 0.386 1.40 0.37 TYP. MAX. 1.60 0.15 1.45 0.45 0.20 12.20 10.20 0.002 0.053 0.012 0.004 0.464 0.386 0.472 0.394 0.315 0.472 0.394 0.315 0.031 0.024 0.039 0.030 0.480 0.401 0.055 0.015 MIN. TYP. MAX. 0.063 0.006 0.057 0.018 0.008 0.480 0.401 inch
OUTLINE AND MECHANICAL DATA
TQFP44 (10 x 10 x 1.4mm)
0(min.), 3.5(typ.), 7(max.)
D D1 A A2 A1
33 34 23 22
0.10mm .004 Seating Plane
E1
B
44 1 11
12
E
B C L K
e
TQFP4410
0076922 D
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STLC3085
Revision history
6
Revision history
Table 11.Document revision history
Date 15-Feb-2006 Revision 1 Initial release. Changes
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STLC3085
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